Order books are swelling across lithography, advanced packaging, and power infrastructure as hyperscalers sprint to build AI capacity. The question for the next 12–18 months isn’t demand—it’s whether the tool chain can deliver, in sequence, without cash-flow hiccups or schedule slips.
Backlog quality: what’s in the pipeline—and how fast can it turn?
ASML’s Q2-2025 results captured the core dynamic. Net sales landed at €7.7 billion with gross margin 53.7%, and net bookings—a forward indicator for the tool pipeline—came in at €5.5 billion, including €2.3 billion of EUV. Crucially, management noted progress in High-NA EUV and confirmed the first shipment of a TWINSCAN EXE:5200B during the quarter. Guidance points to ~15% full-year sales growth with ~52% gross margin, but the company also flagged higher macro/geopolitical uncertainty as it prepares—but does not yet confirm growth for 2026. That nuance matters for any “straight-line” capacity extrapolation. (ASML)
The High-NA handoff from R&D to early customer use is real. Intel has publicly shown its first High-NA tool installed and calibrating in Oregon, while ASML and imec opened a lab to help customers and suppliers de-risk next-gen processes on real hardware. Translation: the pipeline to nodes that will underpin future AI parts—logic first, memory later—is now physical, not just a slide. (Reuters)
What “backlog quality” means now:
- A larger mix of advanced scanners (EUV/High-NA) with long build cycles and deep supplier stacks (ZEISS optics, light sources, precision mechatronics) that are harder to accelerate late in the game. (Zeiss)
- Orders that depend on downstream readiness—if advanced packaging or HBM supply lags, some scanner slots can push, creating timing risk even when end-demand is intact. ASML itself lists order cancellations/push-outs among the standard risks in its release. (ASML)
The tight spots: packaging, interposers/substrates, and HBM
1) Advanced packaging (the bottleneck everyone can see)
TSMC’s 2.5D CoWoS footprint has been the pacing item for AI accelerators; the foundry is expanding monthly CoWoS capacity toward ~70–75k wafers in 2025, roughly doubling 2024 levels, with further growth into 2026. Even with that expansion, industry trackers describe 2025 as tight but improving. This is the bridge between shipped dies and revenue-recognized systems; any slippage here ripples into tool-install ramps up the chain. (TrendForce)
Beyond raw capacity, technology shifts inside CoWoS matter. Silicon-interposer variants (CoWoS-S/L) and reconstituted interposers alter material and process needs; roadmaps anticipate a pivot that eases some interposer constraints but imposes new requirements on redistribution layers and bonding precision. (Greenpeace)
2) Substrates & interposers (the quiet governor)
The AI era is pushing interposers and advanced organic substrates to their limits on line/space and layer count. Engineers call this the “other bottleneck” after packaging capacity. Recent industry deep dives flag:
- Finer RDL targets (≈1–2 µm),
- Hybrid bonding adoption (die-to-die), and
- New multi-material stacks to sustain density.
All three require different tools and suppliers than classic flip-chip flows, which slows sudden capacity swings. (Semiconductor Engineering)
3) HBM supply (tight now, broader in 2026)
On the memory side, HBM3E remains constrained through 2025 even as suppliers add lines. SK hynix has publicly guided to multi-year HBM growth and is reportedly lifting 2025 capex to prepare for 2026 demand; rivals Samsung and Micron are scaling as well. Sell-side and industry trackers see another leg up in 2026 (including new HBM for ASICs) but warn of mix and price volatility as capacity catches up. If HBM availability doesn’t keep pace, AI server shipments (and thus exact timing of tool installations tied to those ramps) can wobble quarter to quarter. (TrendForce, Reuters)
Bottom line: Packaging, substrates/interposers, and HBM are linked constraints. Loosen one without the others and the system still runs near its limit.
Cyclicality risks: demand looks durable, timing less so
At a high level, hyperscaler capex guides are still moving higher into 2H-2025, which supports the litho-to-packaging chain. But there are two cyclical cautions:
- Delivery cadence vs. intent. Even when orders are firm, packaging slots and HBM lots determine when systems ship and revenue converts. This can push tool revenue recognition or service/upgrade timing for ASML and peers.
- Term-premium macro and fab timing. ASML’s CEO explicitly prepares for 2026 growth but won’t confirm it—a nod to macro/geopolitical variables and export regimes. If customer fab build-outs slip or local content rules reshape tool allocations, some orders could move right on the calendar. (ASML)
Read-through to European suppliers: who’s positioned where
ASML (Netherlands) – The central choke point in leading-edge lithography. Q2 showed strong margins and €5.5 billion bookings with EUV/High-NA progress; the company also depends on ZEISS SMT for optics and an extensive European supplier web (including laser and mechatronics specialists). The risk is not demand—it’s sequencing and supplier throughput on the most complex machines ever built. (ASML, Zeiss)
ASM International (Netherlands) – ALD/PEALD for logic (including gate-all-around) and advanced interconnect remains essential to AI-class nodes. Q2-2025 orders were €702 million, down modestly YoY on timing. ASMI’s exposure is node-driven and thus rises with High-NA insertion and leading-edge logic capacity, even if quarterly orders zig-zag with customer timing. (asm.com)
BE Semiconductor—BESI (Netherlands) – Hybrid bonding is moving from pilot to HBM4 and logic volumes. BESI reported strong bookings tied to HBM and logic wins (including orders “from two leading memory producers for HBM4 applications”), making it a direct beneficiary of the chip-stacking trend that raises performance while easing reticle limits. A meaningful portion of AI performance roadmaps now assumes hybrid-bonded assemblies. (Reuters)
Aixtron (Germany) – While not a logic/DRAM toolmaker, SiC/GaN epitaxy sits at the heart of the power side of AI infrastructure—power supplies, PSUs and server power stages are stepping up efficiency. Aixtron’s H1-2025 commentary underscores that SiC tool shipments are a large share of revenue as data-center and EV supply chains keep adding capacity. (Seeking Alpha)
Soitec (France) – The wafer substrate specialist (RF-SOI, Photonics-SOI, FD-SOI) is levered to connectivity and photonics content in data centers and edge devices. FY-2026 Q1 showed softer group revenue on inventory corrections but noted photonics momentum linked to data centers—an AI adjacency that strengthens as optics scale to 800G/1.6T. (GlobeNewswire)
Infineon & STMicroelectronics (Germany/France-Italy) – On the power infrastructure side, Europe’s champions are targeting AI data centers with Si/SiC MOSFETs, BBUs, and silicon-photonics/optics initiatives. Schneider Electric’s updates, plus Infineon/ST releases, confirm that datacenter power and optics are growth vectors—distinct from the litho/packaging bottlenecks but equally essential to turn compute into capacity. (Reuters, infineon.com, ST News)
Grid-to-rack electrics (Schneider Electric, France) – Recent results and partnerships (e.g., NVIDIA collaboration) emphasize sustained DC power demand and AI-ready thermal/electrical systems—evidence that the power tool chain (switchgear, UPS, liquid cooling) is also in “build” mode, particularly in Europe. (Reuters, GlobeNewswire)
How capacity tightness shows up in practice
- Installations vs. start-of-revenue. A fab can accept a scanner, but if downstream packaging/substrate constraints limit die shipment, the customer may stage production ramps—affecting service revenue cadence and upgrade timing for toolmakers.
- Backlog mix affects lead times. EUV and especially High-NA rely on single-source optics and complex subassemblies. ZEISS SMT notes ~1,500 specialists on High-NA optics alone—great for quality, hard to surge on short notice. (Zeiss)
- Price-mix and materials. As CoWoS expands and hybrid bonding proliferates, substrate and interposer specs tighten. SemiEngineering and packaging research groups have warned that pushing line/space and layer counts lifts both tooling demand and risk of yield variability—two reasons the backend is still the rate limiter for many AI SKUs. (Semiconductor Engineering)
What could go right—and wrong—from here
Upside path:
- Packaging ramps land on time (TSMC’s CoWoS targets), HBM supply expands per plan into 2026, and hybrid bonding reaches repeatable high-volume in HBM4/logic. That unlocks a smoother conversion of ASML’s EUV/High-NA backlog into wafer starts and, ultimately, systems revenue. (TrendForce)
Downside path:
- HBM mix or yield hiccups, substrate/interposer constraints, or slower fab construction could push delivery schedules. ASML explicitly cites push-out/cancellation risk in its forward-looking language; memory makers also caution about near-term HBM3E price dynamics as capacity catches up. (ASML, Reuters)
Base case today:
- 2025 stays supply-constrained but loosening, with 2026 the first year when multiple bottlenecks could ease in tandem—if the capex and engineering plans hold.
Ten-day “read-ahead” for operators and observers (non-advisory)
- ASML follow-through: Watch investor Q&A transcripts around EUV/High-NA unit timing and any color on supplier lead-time normalization. (ASML)
- Packaging cadence: Any new CoWoS commentary from foundry or OSAT partners; confirmation that 2025 capacities are on track and 2026 adds are funded. (TrendForce)
- HBM signals: Memory makers’ capex line items and node mix (HBM3E → HBM4), including talk of customer-specific base dies and advanced test/inspection steps—these lock in 2026 supply. (TrendForce)
- Power & optics: Schneider/Infineon/ST updates on AI-ready power, silicon-photonics roadmaps for 800G/1.6T optics—important proof points for the non-silicon “guts” of AI capacity. (Reuters, ST News)
The takeaway
The AI server boom is no longer a single-company story—it’s a chain-of-chains story. At the front end, ASML’s order book and High-NA progress show that the lithography cornerstone is in place. In the middle, CoWoS-class packaging, hybrid bonding, and advanced substrates remain the rate limiters—improving, but still tight through 2025. At the back end, power and cooling vendors in Europe (and globally) are in build-out mode to turn silicon into scalable compute. The prize is large, but the sequencing is unforgiving: to truly keep up with AI demand, each link has to execute on time.
Sources
- ASML Q2-2025 press release (sales, bookings, High-NA shipment, outlook). (ASML)
- High-NA milestones: Intel installation; ASML-imec test lab; ZEISS SMT optics background. (Reuters, Zeiss)
- Packaging capacity: TrendForce on TSMC CoWoS expansion (2025 to ~70–75k wpm; 2026 growth). (TrendForce)
- HBM trajectory: SK hynix HBM/A.I. memory growth outlook; capex lift; ASIC demand mix. (Reuters, TrendForce)
- Hybrid bonding orders: BESI bookings for HBM4/logic applications. (Reuters)
- Interposers/substrates: SemiEngineering on evolving substrate/RDL requirements. (Semiconductor Engineering)
- Power & optics read-through: Schneider Electric data-center demand & NVIDIA partnership; ST silicon-photonics efforts; Infineon AI-power initiatives. (Reuters, GlobeNewswire, ST News, infineon.com)
- Aixtron SiC exposure (context). (Seeking Alpha)
- ASML orders surge (context, Jan 2025). (Reuters)
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